/*
 * Copyright 2019 SiFive, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You should have received a copy of LICENSE.Apache2 along with
 * this software. If not, you may obtain a copy at
 *
 *    https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

package diplomaticobjectmodel.model

import freechips.rocketchip.diplomacy.ResourceBindings
import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, DiplomaticObjectModelUtils}
import freechips.rocketchip.diplomaticobjectmodel.model._
import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCacheMicroParameters}

case class OMInclusiveCache (
  memoryRegions: Seq[OMMemoryRegion],
  nSets: Int,
  nWays: Int,
  blockSizeBytes: Int,
  dataMemorySizeBytes: Int,
  nBanks: Int,
  innerBytes: Int,
  outerBytes: Int,
  _types: Seq[String] = Seq("OMInclusiveCache", "OMCache", "OMDevice", "OMComponent", "OMCompoundType")
) extends OMCache {
  // Unsupported
  def interrupts() = Nil
  def dataECC = None
  def tagECC = None
  def memories = Nil
}
